ASIC​/FPGA Design Engineer

ASIC/FPGA Design Engineer

PGS Worldwide is seeking an ASIC/FPGA Design Engineer in Grand Prairie, TX for a one-year contract-to-hire role supporting a leading aerospace & defense company.

The ASIC/FPGA Design Engineer will support programmable logic design for advanced aerospace and defense systems. This role includes FPGA architecture, RTL development, simulation, verification, hardware-in-the-loop testing, board-level debugging, integration, configuration control, and technical documentation. The position requires FPGA design and verification experience, HDL programming skills, Xilinx/AMD tool experience, and the ability to support complex digital hardware development.

• Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university.
• Bachelor's degree with 6–8 years of relevant experience, or master's degree with 4–6 years of relevant experience.
• 3+ years of professional experience with FPGA design and simulation verification or a related discipline.
• U.S. citizenship required.
• Ability to obtain a DoD Secret clearance.
• Proficiency with HDL programming using VHDL, Verilog, and/or System Verilog.
• Experience with Xilinx/AMD toolsets such as Vivado, Vitis, and Vitis HLS.
• Experience with Ultra Scale design methodology.
• Experience with FPGA simulation tools such as Synopsys VCS.
• Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity.
• Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols.
• Practical lab debug experience using high-speed oscilloscopes, spectrum analyzers, and signal generators.
• Familiarity with Synopsys EDA tools.
• Ability to create test plans, simulation models, and verification environments.
• Ability to collaborate with systems, software, hardware, mechanical, test, manufacturing, and quality teams.

• Define architecture and design specifications for ASIC/FPGA components.
• Write clean, maintainable RTL using VHDL, Verilog, or System Verilog.
• Develop synthesis, place-and-route, and timing closure strategies.
• Create test plans, simulation models, and verification environments using tools such as UVM, SystemC, or Python-based test benches.
• Lead hardware-in-the-loop testing, board-level debugging, and subsystem hardware integration.
• Conduct timing analysis, power budgeting, and resource utilization studies.
• Manage configuration control using Git Lab or equivalent tools.
• Maintain version-controlled repositories and artifact traceability.
• Produce design documentation, including specifications, test plans, verification reports, and release packages.
• Mentor junior engineers and promote best practices in FPGA development, verification, and configuration management.

Pay: $88.99 per hour