Lead Engineer – PWB Layout and Electronic Design Engineer

Job Overview

This position focuses on component placement and routing of highly complex printed circuit boards (PCBs) for avionics products, as well as electronic design activities supporting the design and development of circuit card assemblies for avionics electronic equipment.

Location:

Grand Rapids, MI or Clearwater, FL. Hybrid work arrangement with 2‑3 days in office per week. Relocation package available for eligible candidates.

• Collaborate with design team members including Circuit Design Engineers, Material Scientists, Manufacturing Engineers, and printed wiring board (PWB) suppliers.
• Design high‑density/high‑speed PWBs using complex CAD tools, preferred experience with Siemens/Mentor Expedition.
• Create PWB stack‑ups and via structures that meet design needs and are within supplier capabilities.
• Develop PWB board parts, layout constraints, perform parts placement, routing, and produce fabrication drawings and manufacturing data packages.
• Maintain, improve, and execute Design for Manufacturing & Design rule checks.
• Select components and perform circuit design and schematic capture using CAD tools.
• Conduct electronic testing in a lab environment, including board bring‑up, integration of multiple circuit cards, and pre‑qualification testing.
• Develop and review requirements and perform design analysis for circuit performance using tools such as LTspice, including stress and derating analysis of components.

• Bachelor’s degree in Electrical/Computer Engineering or equivalent experience.
• Minimum 5 years of combined professional experience in PWB layout and circuit design using high‑end CAD tools.
• Knowledge of PWB design and fabrication processes.
• U.S. citizenship or eligible status for U.S. export‑controlled information.

• Strong analytical and critical‑thinking skills.
• Excellent technical writing and communication abilities.
• Experience with Gigahertz microprocessors, FPGA, CPLD, DDR3/DDR4 memory, flash memory, Gigabit Ethernet, and PCIe.
• Experience with mixed‑signal board design (ADCs, DACs, signal conditioning/filtering, analog I/O circuits).
• Experience in High Density Interconnect (HDI) technologies (micro‑vias, buried/blind vias, back‑drilling) for IPC Class 3 boards.
• Experience designing 5+ Gbps serial links (10
  
  GBASE‑KR, PCIe Gen3, Fiber Optics).
• Experience in Power Integrity (PI) and Signal Integrity (SI) simulations, familiarity with Mentor Graphics Expedition Enterprise, Hyperlinx PI/SI, OrCAD PSPICE or LTspice, Mathcad, Microsoft Office, and Visio.
• Experience with VPX, CAN, MIL‑STD‑1553, ARINC 429, ARINC 664, and other MIL/AERO/Avionics standards.

Annual base salary range: $95,000.00 to $ USD. Eligible for an annual discretionary bonus based on a percentage of base salary or commission.

Comprehensive benefits including medical, dental, vision, prescription drug coverage, Health Coach, Employee Assistance Program, 401(k) with company matching, tuition assistance, adoption assistance, paid parental leave, disability and life insurance, and paid time‑off for vacation or illness.

GE Aerospace (General Electric Company) and its affiliates are equal opportunity employers. Employment decisions are made without regard to race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity, age, disability, protected veteran status, or any other characteristic protected by law. GE Aerospace will only employ individuals who are legally authorized to work in the United States.

Posting closes on 8/31/26.