ASIC​/FPGA Design Engineer III, Secret Clearance

Basic Qualifications

• Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
• Prior FPGA development experience.
• HDL programming experience with VHDL, Verilog, and/or System Verilog.
• Active DoD Secret clearance; U.S. Citizenship is required.

Join our team as an ASIC/FPGA Design Engineer where you will work on the development of a sophisticated state‑of‑the‑art avionics product in a world‑class Integrated Product Development environment.

Location:

This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in:

• Sunnyvale, CA
• Denver, CO
• Highlands Ranch, CO

You will be working a flexible 9x80 schedule in the office full‑time.

• Work with low SWaP, radiation‑hardened, space‑rated devices.
• Perform all aspects of ASIC and FPGA development through the lifecycle from initial requirements capture through architecture, design, analysis, simulations and test in a Linux‑based high‑performance computing environment.
• Support technical reviews and present to internal and external stakeholders.
• Interface with an independent verification team that will be working in parallel, verifying the design.

• You need to be an independently minded and well‑organized engineer, comfortable in laboratory digital environments, and able to respond and interact with a dynamic fast‑moving team.
• 3+ years professional FPGA development experience.
• Must have an active DoD Secret or higher clearance; U.S. Citizenship is required.

• Masters Degree.
• Experience in ASIC / FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test).
• FPGA/ASIC verification experience is a plus.
• Experience with electronics design.
• Experience in lab integration and troubleshooting activities.
• Knowledge of space‑grade/qualified FPGAs and ASICs and toolsets including AMD/Xilinx Vivado or Microchip Libero.
• Experience or knowledge of MS Project, JIRA.
• Experience with Earned Value Management System (EVMS).
• Experience mentoring junior engineers.