Senior Pre-Silicon Verification Engineer

About Intel Central Engineering Group

Intel's Central Engineering Group (CEG) is committed to transforming engineering processes while expanding market reach through internal product development and external ASIC design services. Three interconnected pillars drive CEG's mission to enhance Intel's engineering execution and market opportunities, all guided by a data‑driven approach that ensures scalable impact.

We are seeking a Senior Mixed Signal Verification Engineer specializing in clock generator IP verification to ensure functional correctness of PLL/FLL designs. This role combines digital verification expertise with mixed‑signal validation capabilities, requiring collaboration across architecture, RTL development, and analog design teams to deliver high‑quality clock generation solutions.

• Perform comprehensive functional verification of clock generator IPs including PLL/FLL to ensure designs meet specification requirements
• Proactively and independently develop test benches, verification environments, tests, and checkers/assertions ensuring coverage compliance with IP microarchitecture specifications
• Lead Mixed Signal Validation (MSV) activities by running AMS simulations and collaborating cross‑functionally to identify, root‑cause, and resolve schematic bugs

• Replicate, root cause, and debug complex issues in the pre‑silicon environment using systematic debugging methodology
• Maintain and improve existing functional verification infrastructure and methodology for multiple generations of IP test benches
• Document comprehensive test plans and drive technical reviews with design teams

• Collaborate with architects, RTL developers, and analog schematic owners to improve verification of architectural and microarchitectural features
• Participate actively in the definition of architecture and microarchitecture features of the IP being designed
• Participate in RTL development activities and contribute to design optimization

• Understanding of mixed‑signal design principles and AMS simulation techniques
• Knowledge of clock generation architectures and timing analysis
• Familiarity with analog verification methodologies and tools
• Experience with clock domain crossing verification and analysis

• Strong analytical and problem‑solving skills for complex verification challenges
• Ability to work independently while collaborating effectively across multiple teams
• Excellent documentation and communication skills for technical reviews

• Bachelor's degree in Electronics/Electrical/Computer Engineering
• 3+ years of experience in Design Verification and Validation methodologies with UVM, System Verilog, and industry‑standard EDA tools
• 3+ years of experience in scripting languages such as Python and Perl

• Post‑graduate degree in Electronics/Electrical/Computer Engineering
• Experience with debug methodologies
• Experience with RTL development and design implementation
• Experience working on PLL/FLL or SoC clocking architectures and verification

• Opportunity to work on cutting‑edge clock generation technologies and mixed‑signal verification
• Collaboration with world‑class engineers in architecture, design, and verification
• Access to advanced EDA tools and verification infrastructure
• Professional development in mixed‑signal verification and clock design
• Direct impact on Intel's IP portfolio and engineering execution excellence

Experienced Hire

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The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on…