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Semiconductor Manufacturing & Architecture Analyst

Job in Hillsboro, Washington County, Oregon, 97104, USA
Listing for: SemiAnalysis
Full Time position
Listed on 2026-04-18
Job specializations:
  • Engineering
    Electrical Engineering, Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Position Overview

We are seeking an experienced, clever and motivated Semiconductor Manufacturing & Architecture Analyst to join our team in the United States. This role is responsible for the hands-on analysis of manufacturing innovations related to AI and datacenter products, from the system level down to the transistor. This role requires a mix of technical expertise, sensibility, and autonomy. You’ll need to work independently, collaborate across our globally distributed team, and deliver insights on cutting edge manufacturing process and design choices, optimizations, and trade-offs.

Responsibilities
  • Conduct detailed architecture, manufacturing, integration, and process analysis of AI and datacenter hardware (e.g., GPUs, ASICs, CPUs, and associated systems).
  • Analyze and document semiconductor manufacturing processes, including FEOL, BEOL, and advanced packaging techniques, based on physical inspection and acquired data.
  • Identify competitive advantages, disadvantages, and generational changes based on these findings.
  • Monitor and report on trends in semiconductor technology, process development, and device research.
  • Perform as a recognized authority in the current state of the art in AI and datacenter process architectures.
  • Work with design experts and market analysts to develop actionable market insights and reports.
Requirements
  • 3+ years of industry experience in packaging, BEOL, or FEOL engineering or a reasonably equivalent role, e.g. as a Reliability Engineer, Hardware Engineer, Debug Engineer, Process Integration Engineer, or Failure Analysis Engineer.
  • Direct experience in the broad areas of design, debug, physical failure analysis, electrical failure analysis, or fault isolation.
  • Functional knowledge of process integration or product architecture on advanced nodes.
  • Understanding of Design Technology Co-Optimization (DTCO) principles and their application.
Preferred Skills
  • Experience in integration, process or design R&D related to advanced packaging (e.g., 2.5D/3D), high-speed interconnects, and general advanced compute.
  • Broad understanding of advanced manufacturing processes across CMOS logic, memory (HBM, GDDR), networking, and emerging technologies.
  • Hands-on experience with sample prep and analytical tools, SEM, (P)
    FIB, STEM, EMMI/IREM, BIRCH, nanoprobing, etc.
  • Proven ability to interpret analytical data, such as micrographs and materials, to infer process and design characteristics.
  • Familiarity with Python for data analysis and complex engineering tasks.
  • Strong professional network of experts with whom you comfortably and regularly communicate.
  • Strong organizational skills and an understanding of statistics and process controls.
Growth Areas
  • Deepen expertise in next-generation semiconductor nodes (e.g., sub-3nm, gate-all-around architectures) and their system-level implications.
  • Expand capabilities in advanced packaging innovations such as chiplets, heterogeneous integration, and 3D stacking.
  • Develop stronger cross-domain knowledge across compute, memory, and interconnect ecosystems to drive holistic system insights.
  • Enhance proficiency in data-driven analysis, including Python-based workflows, automation, and statistical modeling for failure analysis and process optimization.
  • Build thought leadership through publications, industry engagement, and collaboration with leading experts across semiconductor and AI infrastructure domains.
  • Progress toward becoming a subject matter expert influencing both technical direction and market-facing insights within the organization.
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