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Senior ASIC Timing Engineer

Job in Hillsboro, Washington County, Oregon, 97104, USA
Listing for: NVIDIA
Full Time position
Listed on 2026-05-06
Job specializations:
  • Engineering
    Manufacturing Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 136000 USD Yearly USD 136000.00 YEAR
Job Description & How to Apply Below

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team.

What You'll Be Doing
  • Drive Timing Analysis and Closure:
    Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.
  • Collaborate with Cross-Functional Teams:
    Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs.
  • Contribute to Cutting-Edge Projects:
    Play a pivotal role in the success of our innovative projects and advancement of our technology. Leverage your expertise to improve timing convergence flows in collaboration with methodology teams.
What We Need To See
  • BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 3 years’ experience in Timing and STA
  • Hands‑on experience in full‑chip/sub‑chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
  • Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
  • Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
  • Expertise and in‑depth knowledge of industry standard STA and timing convergence tools.
  • Knowledge of deep sub‑micron process nodes and hands‑on experience in modeling and converging timing in these nodes.
Ways To Stand Out From the Crowd
  • Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs
  • Background in logic synthesis and equivalence checking/FV.
  • Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
  • Understanding and timing closure of digital logic/macros in AMS designs/IPs.
  • Experience in methodology and/or flow development as well as automation.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $136,000 USD – $218,500 USD for Level 3, and $168,000 USD – $264,500 USD for Level 4. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse work environment and prides itself as an equal opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Position Requirements
10+ Years work experience
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