Hardware Design Engineer

Responsibilities

• Design architecting and trade-off analysis
• RTL coding and verification
• Memory Controller + PHY integration and verification
• Customer delivery and support

Strong System Verilog/Verilog RTL design expertise

• Questa/Incisive/VCS simulator experience
• Python/Perl/Tcl scripting experience
• Significant ASIC and/or FPGA design experience
• Ability to learn quickly and work independently
• Solid communication and project management skills
• 5+ years of logic design experience
• BSEE

• ASIC synthesis, timing constraint, CDC/RDC experience
• Verification experience
• Memory (HBM, GDDR, LPDDR, DDR) expertise
• AMBA AXI or CHI design experience
• Located in the Hillsboro, Oregon area

• Provided as needed