Post-silicon Validation and Debug Engineer

Intel is shaping the future of technology to help create a better world. In our Client Computing Group (CCG), services and data reside in scalable data centers and are accessible over the Internet. This role focuses on designing and optimizing processors, chipsets, and other hardware for consumer devices while also enhancing the software ecosystem, including drivers and utilities.

We seek a highly motivated and experienced Post‑Silicon Validation Engineer to ensure the quality and functionality of cutting‑edge CPU products for laptops, desktops, and gaming systems. The engineer will validate complex CPU/SOC architectures and help meet the highest standards of reliability and performance.

• Develop and execute validation plans to verify CPU/SOC functionality, power and thermal management across multiple silicon platforms.
• Design, implement, and debug validation tests and methodologies for post‑silicon environments.
• Collaborate with cross‑functional teams—design, firmware, software, and manufacturing—to identify and resolve issues.
• Analyze and debug CPU/SOC and system‑level issues using advanced tools and methodologies.
• Lead debug task forces to root‑cause and resolve issues impacting program milestones.
• Mentor junior validation engineers in their technical development.
• Drive validation automation, coverage improvement, and process efficiency for validation execution.
• Work with internal stakeholders to ensure smooth integration and delivery of products to market.

• Strong written and verbal communication skills.
• Ability to prioritize multiple projects and work independently.
• Effective collaboration in a cross‑functional environment.
• Excellent problem‑solving and debugging skills.

• Bachelor’s degree with 3+ years of experience or master’s degree with 6+ months in electrical engineering, computer engineering, computer science, or a related discipline.
• 1+years of hands‑on experience in post‑silicon validation, pre‑silicon verification, or design, particularly in CPU, SOC, or chipset domains.
• 1+years of experience with SOC and CPU architecture, microarchitecture, and power‑management flows.
• 1+years of scripting and programming experience (Python, C/C++, or Perl) to develop validation tools and frameworks.
• 1+years of experience with silicon validation tools, lab equipment (logic analyzers, oscilloscopes), and debugging techniques.

• 2+years of experience with graphics, media, display IPs architecture, microarchitecture, and power‑management flows.
• Advanced degrees and 5+years of experience encouraged.
• Familiarity with power and performance testing methodologies.
• Experience with Intel architecture, silicon bring‑up, and validation flow.
• Knowledge of firmware and software interaction with hardware.

Experienced Hire. Shift 1 (United States of America). Primary

Location:

US, Oregon, Hillsboro. Additional Locations: US, California, Folsom.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Competitive pay, stock bonuses, and benefit programs including health, retirement, and vacation. Detailed benefits information is available on Intel’s career site.

$ – $ USD (US locations). Individual pay is determined by location and other factors.

This role will require an on‑site presence.

Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. No fees are charged during the hiring process. If asked to pay any fees, report immediately to the recruiter.