LTD Process Development Integration Engineer

Overview

As a Process Integration Development Engineer, you will play a pivotal role in advancing Intel's Logic Technology Development (LTD), contributing to the design and execution of innovative semiconductor manufacturing processes that maintain Intel's leadership in computing technology. Your work will directly impact Intel's ability to scale advanced silicon technologies from research to high-volume manufacturing, ensuring quality, reliability, and performance. By collaborating across teams to develop integrated process solutions, your contributions will drive Intel's goal of delivering world‑class yields and advancing Moore's Law.

• Lead Quality Event Form (QEF) responses and Disposition/Material Review Board (XRB) actions in coordination with module and manufacturing teams.
• Perform fab and E‑test parameter trending, process control, and statistical analysis (including ANOVA) to identify issues, opportunities, and corrective action plans.
• Monitor Yield Cliffs and Product Performance Indicators.
• Conduct data‑driven root cause analyses of fab quality events and partner with stakeholders to implement preventative solutions.
• Drive process variation reduction through deep understanding of semiconductor processes and applied statistics.
• Develop and implement process targeting strategies to optimize product performance and yield.
• This is a Shift 7 compressed work week (CWW) engineering position, working on Thursday, Friday, Saturday, and every other Wednesday 7 am – 7 pm.

• Bachelor’s degree in electrical engineering, physics, material science and engineering, computer science, chemical engineering, mechanical engineering, nuclear engineering, optics, or chemistry (with focus on hands‑on experimental research).
• 1 + years of prior semiconductor industry experience.
• 6 + months of experience with statistical data analysis tools, including JMP, Excel, or MATLAB.
• 6 + months of experience with root cause analysis and corrective action planning (CAPA) during quality events.

• Experience with semiconductor processing fundamentals, including lithography, etching, chemical and mechanical polishing, and related processes.
• Demonstrated knowledge of transistor device physics and experimental design principles.
• Familiarity with materials characterization techniques such as SEM, TEM, and metrology.
• Exposure to statistical data analysis tools, including JMP, Excel, or MATLAB.
• Experience with root cause analysis and corrective action planning (CAPA) during quality events.
• Research experience in STEM fields, particularly semiconductor device architectures.
• Proficiency in model‑based problem‑solving techniques to address complex engineering challenges.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Work model:
On‑site presence required.

Shift: 7 (United States of America). Primary

Location:

US, Oregon, Hillsboro.