Senior Testchip SoC Physical Design Engineer; Integration & Methodology

About The Role

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X‑Chip SoC Full‑Chip Integration team. This team plays a critical role in enabling next‑generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high‑volume manufacturing readiness.

• Develop layout design methodology for testchip development in next generation process nodes
• Work closely with Process Integration, Yield and QnR to define critical design features that need to be exercised in the early lead vehicle test chips
• Establish, orchestrate, oversee, and maintain hierarchical layout design specifications for correct‑by‑construction integration
• Build and execute tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
• Drive all aspects of physical design convergence, including preparing layout hierarchy for design tape‑in, debugging and resolving issues uncovered by verification tools
• Work with tool/flow owners and vendors for ongoing tool/methodology improvement

• Strong interest in layout design in advanced technology nodes
• Strong verbal and written communication skills
• Ability to work well both autonomously and in an intensive, cooperative team environment
• Coordinate between different stakeholders to arrive at execution commit for testchip
• Motivation to continuously learn and push improved layout productivity and efficiency

• Work on cutting‑edge semiconductor technologies that shape the future of computing
• Collaborate with industry‑leading experts across design and manufacturing
• Opportunities for career growth and technical leadership
• Contribute to innovations that impact global technology at scale
• Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life

• Master’s degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:
• Experience with physical/layout design in advanced technology nodes
• Experience with layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler
• Knowledge of design rules and layout constraints in advanced semiconductor processes
• Experience with floor planning, hierarchical design integration, and layout verification/debug

• Experience in definition of testchip/product design from concept to execution commitment
• Experience working with foundry teams on negotiating features to exercise in design
• Proven project management skills coordinating and tracking the entire design cycle of a project from feature definition to final tape‑in
• Previous related work experience in a semiconductor foundry preferred

Experienced Hire

Shift 1 (United States of America)

Primary: US, Oregon, Hillsboro
Additional: US, California, Santa Clara; US, Texas, Austin

We offer a total compensation package that ranks among the best in the industry. It includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Find out more about the benefits of working at Intel.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. We do not charge any fees during the hiring process. Candidates should report any requests to pay fees immediately to their recruiter.

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Position of Trust: N/A