Physical Design Engineer Core IP

Job Details

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)
Primary

Location:

US, Oregon, Hillsboro

Intel is shaping the future of technology to help create a better future for the entire world. Our work in AI, analytics, and cloud‑to‑edge technology powers countless innovations. As a member of Intel’s CPU development team, you will help design the latest core IP to power cutting‑edge compute processors across client, server, IOTG and AI, focusing on power efficiency.

• Performs physical design implementation of custom CPU designs from RTL to GDS, creating a design database ready for manufacturing.
• Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Performs verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
• Analyzes results and makes recommendations to improve current and future CPU microarchitectures, collaborating closely with logic, circuit, architecture, and design automation teams.
• Possesses CPU‑specific expertise in structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
• Works with industry EDA vendors to build and enhance tool capabilities for a high‑speed, low‑power synthesizable CPU.
• Optimizes CPU design to improve product‑level parameters such as power, frequency, and area.
• Participates in developing and improving physical design methodologies and flow automation.

Minimum Qualifications

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or related field with 3+ years of relevant work experience, or an M.S. degree with 2+ years of relevant work experience.
• 2+ years’ experience in synthesis of a digital logic block or partition.
• 2+ years of experience in each of the following: integrated circuit design tools (e.g., Synopsys/Cadence), logic synthesis, place and route, static timing analysis, and design closure.
• Experience with PV convergence (static timing and power analysis), chip physical design verification (formal equivalence, timing, electrical rules, DRC/LVS, noise and electro‑migration checks).
• Proficiency in scripting in an interpreted language (minimum TCL plus at least one of Perl, Python, Ruby).

Preferred Qualifications

• Strong knowledge of physical design best practices concerning floor‑planning, routing techniques, and clock distribution.
• Strong knowledge of static timing analysis, noise analysis, and reliability verification techniques.
• Familiarity with RTL‑to‑GDS methodologies and formal equivalence.
• Experience with Synopsys tool suite (Fusion compiler, ICC2, Prime Time) or Cadence (genus/innovus).
• Experience performing CPU‑level timing analysis and optimization, generating and verifying timing constraints while addressing timing violations at chip or block level for CPU cores.
• Experience working closely with the clocking team and full‑chip designers to balance timing fixes, power delivery, clocking, and partitioning.

Our total rewards package includes competitive pay, stock bonuses, and benefits such as health, retirement, and vacation. The annual salary range for this role in the United States is $–$ USD. Additional benefits details are available on Intel’s careers website.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.