Senior Chip Physical Design Integration Lead

Job Details

Join Intel as SOC Physical Design Engineer, where you will play a pivotal role in shaping the future of custom IP and SoC designs. In this position, you will drive the physical design implementation of cutting‑edge technologies, transforming RTL to GDS databases ready for manufacturing. Your expertise in physical design flows will directly contribute to optimizing power, frequency, and area metrics, enabling Intel to deliver high‑performance products that empower innovation worldwide.

This is an opportunity to be part of a dynamic team where your work will have a meaningful impact on Intel’s mission to push the boundaries of technology and deliver industry‑leading solutions.

• Work on SOC floorplan, pin and macro placement optimizing area and efficiency.
• Perform physical design implementation for custom IP and SoC designs across the entire design flow, including synthesis, place and route, clock tree synthesis, floor planning, and static timing analysis.
• Conduct verification and sign‑off activities such as formal equivalence verification, reliability verification, power integrity analysis, and layout verification using industry‑standard EDA tools.
• Drive design optimization across multiple power domains, static and dynamic power integrity analysis, and structural design checking.
• Participate in the development and enhancement of physical design methodologies and flow automation.
• Collaborate with cross‑functional teams to ensure designs meet product‑level parameters, quality benchmarks, and are ready for manufacturing.

Minimum Qualifications

• Bachelor’s degree with 8+ years or master’s degree with 6+ years or PhD with 4+ years in Electrical/ Electronic Engineering, Computer Engineering, Computer Science or related disciplines.
• 4+ years of experience with the following technical skills:
  • Proficiency in physical design flows, including synthesis, place and route, clock tree synthesis, and static timing analysis.
  • Expertise in design optimization for physical design, multi‑power plane design (MPP/UPF), and RTL to GDS workflows.
  • Hands‑on experience with scripting to automate design flows.
  • Knowledge of EDA tools and methodologies for verification, reliability, timing closure, and power integrity analysis.

Preferred Qualifications

• Expertise in design planning, hierarchical design, SOC floorplan and optimizations.
• Strong analytical skills and ability to resolve complex design challenges efficiently.
• Effective communication skills and collaborative teamwork.
• Experience developing and improving physical design methodologies and automation tools.
• Familiarity with industry trends and emerging technologies in physical design, ensuring forward‑thinking and innovative designs.

Experienced Hire

Shift 1 (United States of America)

Primary: US, Massachusetts, Beaver Brook
Additional: US, Oregon, Hillsboro

Data Center Group (DCG) – focused on delivering exceptional products across data center solutions, including Xeon‑based and custom x86 products.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.

We offer a total compensation package that ranks among the best in the industry, including competitive pay, stock bonuses, and benefits such as health, retirement, and vacation. Annual Salary Range for US jobs: $ –  USD.

Hybrid work model allowing employees to split time between on‑site and off‑site work.

Intel is committed to Responsible Business Alliance compliance and ethical hiring practices. No fees are charged during the hiring process. Report any fees requested during recruitment.