Physical Design Engineer

Job Overview

In this position you will develop and support mixed‑signal and custom digital hard IPs.

The job will entail: generating hard IP collateral for SOC consumption, verifying collateral quality, providing collateral support to SOC customers, verifying digital timing performance, noise analysis, logic equivalence, power characterization, netlist support of layout tasks, and analysis of late‑changing process.

• Develop and support mixed‑signal and custom digital hard IPs.
• Generate hard IP collateral for SOC consumption.
• Verify collateral quality.
• Provide collateral support to SOC customers.
• Verify digital timing performance, noise analysis, logic equivalence, and power characterization.
• Support netlist for layout tasks and analyze late‑changing process.

• Bachelor’s degree in Electrical Engineering or Electrical and Computer Engineering. More advanced degrees preferred.
• 3+ years of experience in the field.
• Experience with static timing analysis tools, custom analog simulation, Cadence schematic entry, and familiarity with mixed‑signal circuits such as analog IO, PLL, clock generation, analog‑to‑digital converters, and LDO voltage regulators.
• Strong verbal and written communication skills.
• HS diploma or GED equivalent required for U.S. candidates.

All information will be kept confidential according to EEO guidelines.