IP Design Verification Engineer

Job Details

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives.

Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products? If so, come join us to do something wonderful.

As an IP Verification Engineer, you will be working on UCIe Mixed‑Signal IP delivering to multiple Server SoCs.

• Analytical and problem‑solving skills
• Verbal/written communication skills
• Effective team player with continuous learning mindset
• Willingness to balance multiple tasks
• Willingness to work in a fast‑paced environment and have as much fun and growth as possible in the process

• Test bench development, directed/constrained random test generation in UVM
• Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
• Run RTL and gate level functional verification, debug failures, and analyze coverage
• Support mixed‑signal verification using Verilog models of analog IP

• The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience – OR – Master’s degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience – OR – PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
• Relevant Work experience include:
  • IP or SoC verification experience using System Verilog/UVM
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
  • Implementation of verification environments that include use of constrained‑random stimulus
  • Code/Functional Coverage analysis
  • Writing System Verilog Assertions (SVA)

• Mixed‑Signal Verification
• Experience with UCIe or PCIe or I/O

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, Oregon, Hillsboro

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $ -  USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training.

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.