Process Integration Development Engineer - Defect Metrology

Overview

Intel’s Logic Technology Development (LTD) leads the semiconductor industry in scaling and advancing process technology, enabling Moore's Law to continue. Defect Metrology plays a key role by identifying, characterizing, and reducing defects that impact yield and performance in advanced silicon processes. This role supports the transition from research to high-volume manufacturing by creating defect reduction roadmaps and working with integration and yield teams.

• Lead yield and defect reduction efforts using state-of-the-art metrology tools and QtMs.
• Organize and present defect summaries to LTD engineering teams.
• Partner with Intel integration, yield, and failure analysis labs to provide root cause analysis for defect issues.
• Implement ramp to manufacturing volumes demonstrating technology meets requirements and transfer the technology to manufacturing via Copy Exactly Methodology.
• Hold the team and collaborators accountable for quality through IMT and FTs.
• Collaborate as part of the TD defect metrology group and model a team culture of trust, collaboration, safety, accountability, and excellence.
• Build strong relationships with other LTD process and design teams.

Minimum Qualifications:

• Master’s degree with 3+ years of experience or PhD with 1+ year of experience in Computer Science, Physics, Materials Science and Engineering, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Nuclear Engineering, Optics, or Chemistry focused on hands‑on experimental research.
• At least 1 year of experience in materials characterization (SEM, TEM, etc.), materials fabrication, synthesis, metrology, or statistical/data analysis (MATLAB, Excel, JMP, etc.).
• Semiconductor processing fundamentals (lithography, wet/dry etch, polishing, device physics) and design of experiments.

Preferred Qualifications:

• Experience with Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
• Expertise in semiconductor physics and processing.
• Yield or defect improvement experience using Brightfield, Darkfield, or Voltage Contrast microscopy.
• Defect troubleshooting with tools such as Klarity, JMP, Model‑Based Problem Solving (MBPS), or Fishbone Analysis.

Job Type: Experienced Hire

Shift: Shift 1
Primary

Location:

US, Oregon, Hillsboro
Additional Locations: N/A

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identity, gender expression, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Competitive salary range: $115,110–219,550 USD (US). Compensation includes base pay, stock bonuses and benefit programs such as health, retirement, and vacation.

Hybrid model: split time between on‑site and off‑site work.