Speed PHY System Architect

Job Details

Job Description:

• Develop and drive analog and mixed‑signal IP architectures, signal processing algorithms, and calibration algorithms for system‑on‑chip (SoC) independent AMS IPs.
• Conduct top‑down architectural analysis of AMS systems and perform transistor‑level feasibility studies for various AMS circuits.
• Design novel architectures and define microarchitectures for next‑generation AMS IP to achieve optimal performance, power, and area for diverse product segments.
• Enhance system performance by leveraging digitally assisted analog techniques and optimizing the partitioning of analog and digital circuits.
• Evaluate trade‑offs, explore innovative approaches, and provide proof‑of‑concept design alternatives for AMS systems.
• Collaborate with IP design and verification teams to define, develop, and validate robust AMS IPs for SoC integration.
• Support SoC architects, design engineers, and verification engineers in selecting, configuring, and validating SoCs that leverage AMS IPs.
• Perform modeling, simulation, and optimization for power, area, and performance metrics, analyzing test results to identify improvement opportunities.
• Define future AMS IP technology targets by influencing cross‑functional roadmaps and reviewing emerging technology trends.

• Strong communication and collaboration skills, with the willingness to mentor and technically guide team members.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM field with 9+ years of experience.
• OR Master's degree in Electrical Engineering, Computer Engineering, or related STEM field with 6+ years of experience.
• OR PhD in Electrical Engineering, Computer Engineering, or related STEM field with 3+ years of experience.
• Experience listed above should be a combination of the following:
• Analog and mixed‑signal circuit design within standard CMOS technologies, including op‑amps, comparators, bandgap references, and linear regulators.
• Backend verification tools such as Monte Carlo simulations, EMIR, and static/dynamic MOSFET voltage checks.
• Analog behavior modeling and system‑level understanding of AMS circuits.
• Hands‑on experience with transmission line theory and AMS system modeling.
• Architectural feature definition, high‑speed design techniques, and IP architecture definition.
• Proven experience with high speed PHY designs from concept through qualification.

• Proficiency in MATLAB or similar tool‑base modeling.
• Experience in post‑silicon debugging and high‑volume productization of designs.
• Familiarity with signal integrity and power integrity analysis.
• Background in analog layout techniques, including floor‑planning, matching, shielding, and parasitic optimization.

Experienced Hire

Shift 1 (United States of America)

US, California, Santa Clara

US, Oregon, Hillsboro

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

N/A

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $ -  USD

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.