Director, Process Engineer – Dry Etch

Job Overview

Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider. The Manufacturing Development and Customer Engineering (MDCE) organization leads this shift by improving yield, performance, and customer service across Intel’s technology nodes. We are seeking a Director, Process Engineer – Dry Etch to drive technology development, process capability, and manufacturability in advanced CMOS technologies through plasma, reactive ion, atomic layer, conductor, dielectric, and thermal etching processes.

• Lead dry etch process engineering to meet high-volume manufacturing (HVM) requirements, focusing on safety, quality, performance, throughput, process capability, and mandating lower defectivity, improved yield, and reduced cost.

• Define and execute process experiments, analyze data, troubleshoot tools and process issues, and collaborate with cross‑functional stakeholders to deliver robust etch solutions aligned with Intel’s technology roadmap.

• Partner with Integration, Lithography, Thin Films, Cleans, Yield, Defect Metrology, Yield, Quality and Reliability, and supplier teams to provide modular solutions that support technology targets.

• Sustain and optimize dry etch processes across multiple technology nodes, driving critical dimension control, profile control, uniformity, selectivity, chamber matching, defectivity, and throughput improvements.

• Manage HVM enablement activities including process transfer, ramp readiness, excursion response, tool qualification, recipe optimization, and manufacturing health improvements.

• Document process learning, experimental results, best‑known methods, control plans, and transfer requirements accurately and clearly.

• Minimum 10+ years of semiconductor experience focused on dry etch process development, integration, or HVM support;
  Master’s degree in a related technical discipline.
• Hands‑on experience with plasma etch equipment, recipe optimization, process characterization, and troubleshooting; history of cross‑module collaboration.
• Strong problem‑solving skills with structured methodologies, data analysis, and engineering judgment.
• Excellent written and verbal communication; ability to present technical information clearly to diverse audiences.
• Behavioral traits: technical depth, execution discipline, collaboration, initiative, detail orientation, pressure handling, and industry knowledge.

• Doctoral degree in a related field is a plus.
• Substantial technical background in advanced CMOS dry etch, advanced logic, or high‑scaled interconnect technologies.
• Experience delivering process improvements in technology development, transfer, ramp, or HVM.
• Experience with advanced logic technologies such as Gate‑All‑Around (GAA) or advanced patterning.
• Experience partnering with equipment suppliers on chamber matching, hardware improvements, productivity, defectivity, and process capability.
• Proficiency in data analysis, statistical process control, and design of experiments.
• Knowledge of metrology and inspection data such as CD‑SEM, profile metrology, defect inspection, overlay, electrical test, or yield data.

Experienced Hire – Shift 1 (United States);
Primary

Location:

Hillsboro, Oregon. Additional location:
Phoenix, Arizona.

Annual Salary Range: $ – $ USD. Total compensation includes competitive pay, bonus opportunities, stock awards, and a comprehensive benefits package (medical, life and disability insurance, wellness programs, time off, and other reward programs).

Position of Trust – background investigation required. This position is a Position of Trust and will require an extensive background investigation.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender, gender identity, gender expression, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, or any other characteristic protected by applicable law.