Junior Physical Design Engineer; CPU

Job Description

About the Role

Join a team developing next‑generation CPU cores that power client, server, IoT, and AI platforms. As a Junior Senior Physical Design Engineer (CPU), you will contribute to cutting‑edge silicon design using advanced process technologies and work alongside experienced engineers to support implementation from RTL to GDS, gaining hands‑on experience in high‑performance, power‑efficient processor design.

• Support physical design execution for CPU core or subsystem blocks under guidance
• Assist with synthesis, place and route (PnR), and physical verification tasks
• Perform analysis for timing, power, and design rule compliance
• Debug and resolve design issues with mentorship from senior engineers
• Contribute to script and flow development (e.g., TCL, Python)
• Collaborate with cross‑functional teams including RTL design, verification, and full‑chip integration
• Document design work and contribute to best practices and design flows

• Strong learning agility and curiosity
• Pays close attention to detail and quality
• Communicates clearly and effectively in a team environment
• Demonstrates adaptability and openness to feedback
• Builds collaborative relationships across teams

• Work on cutting‑edge CPU core designs that power client, server, IoT, and AI platforms used worldwide
• Be part of a team driving innovation at advanced semiconductor process nodes
• Contribute across the full RTL‑to‑GDS flow, gaining exposure to complex, high‑impact silicon design
• Collaborate with experienced engineers across architecture, design, and full‑chip integration
• Grow technical expertise through challenging problems, modern tools, and continuous learning opportunities
• Join a culture that values inclusion, collaboration, and diverse perspectives while delivering industry‑leading technology

• Bachelor’s in Computer / Electrical Engineering or related field with 2+ years of educational or work experience, or a master’s with 3+ months of educational experience
• Experience with integrated circuit design tools (e.g., Synopsys/Cadence) including logic synthesis, place and route, static timing analysis and design closure
• Experience with PV convergence (including static timing and power analysis)
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electromigration checks
• Scripting in an interpreted language, minimum TCL and at least one other (e.g., Perl, Python, Ruby)
• Experience with one or more of the following areas:
  • Synthesis of a digital logic block integrated into a large SoC or IP

• Physical design best practices concerning floor‑planning, routing techniques, clock distribution
• Static timing analysis, noise analysis, and reliability verification techniques
• RTL‑to‑GDS methodologies and formal equivalence
• Familiarity with Synopsys tool suite (Fusion compiler, ICC2, Prime Time) or Cadence (genus/innovus)

• Job Type: College Grad
• Shift: Shift 1 (United States of America)
• Primary
  
  Location:
  
  US, Oregon, Hillsboro

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Intel invests in our people and offers a complete and competitive package of benefits for employees and their families through every stage of life. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $– USD