Senior Testchip SoC Physical Design Engineer; Integration & Methodology

About the Role

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X‑Chip SoC Full‑Chip Integration team. This team plays a critical role in enabling next‑generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high‑volume manufacturing readiness. In this role, you will contribute to the development of physical design methodologies and drive full‑chip SoC integration for cutting‑edge testchip vehicles, collaborating across design, process, and manufacturing teams to ensure high‑quality, scalable solutions for advanced technology nodes.

• Develop layout design methodology for testchip development in next generation process nodes
• Work closely with Process Integration, Yield and QnR to define critical design features that need to be exercised in the early lead vehicle test chips
• Establish, orchestrate, oversee, and maintain hierarchical layout design specifications for correct‑by‑construction integration
• Build and execute tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams
• Drive all aspects of physical design convergence, including preparing layout hierarchy for design tape‑in, debugging and resolving issues uncovered by verification tools
• Work with tool/flow owners and vendors for ongoing tool/methodology improvement

• Exhibit strong interest in layout design in advanced technology nodes
• Strong verbal and written communication skills
• Ability to work well autonomously and in a cooperative team environment
• Coordinate between stakeholders to arrive at execution commit for testchip
• Motivation to continuously learn and improve layout productivity and efficiency

• Work on cutting‑edge semiconductor technologies that shape the future of computing
• Collaborate with industry‑leading experts across design and manufacturing
• Opportunities for career growth and technical leadership
• Contribute to innovations that impact global technology at scale
• Intel offers a complete and competitive benefits package for employees and their families

Minimum qualifications: Master’s degree in electrical engineering or related field with a minimum of 5 years’ experience in:

• Physical/layout design in advanced technology nodes
• Layout design tools such as Cadence Virtuoso Suite or Synopsys Custom Compiler
• Design rules and layout constraints in advanced semiconductor processes
• Floor planning, hierarchical design integration, and layout verification/debugging

Preferred qualifications: Experience in definition of testchip/product design from concept to execution commit, experience negotiating features with foundry teams, proven project‑management skills coordinating the design cycle from feature definition to final tape‑in, and previous work experience in a semiconductor foundry.

Experienced Hire – Shift 1 (United States). Primary location:
Hillsboro, Oregon. Additional locations:
Santa Clara, CA and Austin, TX.

Annual salary range: $141,910–$200,340 USD. Compensation includes competitive pay, stock bonuses, and benefit programs covering health, retirement, and vacation.

Work Model:
Hybrid – employees may split time between on‑site and off‑site work.

Note:

For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.