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Senior RTL/Logic Design Engineer — Hybrid Datacenter IP
Job in
Hillsboro, Washington County, Oregon, 97104, USA
Listed on 2026-07-28
Listing for:
Intel
Full Time
position Listed on 2026-07-28
Job specializations:
-
Engineering
Systems Engineer
Job Description & How to Apply Below
Intel's UCIE PHY IP team in California (Santa Clara) is seeking an experienced senior Logic design engineer to contribute to RTL coding and verification for flagship datacenter/server designs. You will develop the logic design, RTL coding, and simulation for IP blocks.
Key responsibilities include defining architecture features, performing quality checks, and optimizing logic for power, performance, area, and timing.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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