Senior PCIe IP Design Lead (RTL/SystemVerilog
Job in
Hillsboro, Washington County, Oregon, 97104, USA
Listed on 2026-08-08
Listing for:
Rambus
Full Time
position Listed on 2026-08-08
Job specializations:
-
Engineering
Electronics Engineer, Hardware Engineer, Systems Engineer
Job Description & How to Apply Below
Rambus in the United States is seeking a motivated Principal Design Engineer to join the PCIe IP design team. You will contribute to architecture and micro-architecture and implement designs in System Verilog, collaborating with an international team.
The role involves prototyping IPs on cutting-edge FPGAs, supporting existing IP generations, and working in a hybrid environment with three onsite days per week. A strong RTL background and Masters/PhD are preferred.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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