Principal SI​/PI Engineer - 18231

Principal Si/Pi Engineer

We are open to hiring in Austin, Hillsboro, and the Bay Area as well.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars, machine learning to artificial intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

We develop and deliver industry-leading high-speed interface IP and system solutions, enabling customers to build reliable, high-performance products across advanced nodes and packaging technologies.

You are a highly skilled and passionate engineer with a deep understanding of high-speed signal and power integrity, particularly in the realm of Ser Des interfaces. With a proven track record in end-to-end SIPI for advanced links such as PCI Express (Gen6/7/8), E224G, E448G, and CXL (over PCIe), you thrive on solving complex engineering challenges and collaborating across cross-functional teams. You have a strong foundation in electromagnetic theory, transmission lines, and advanced modeling, and you are adept at translating system requirements into actionable, measurable signoff criteria.

Your expertise spans both theoretical and practical realms: you are comfortable with channel modeling, frequency and time domain analysis, and using state-of-the-art simulation and measurement tools. You bring hands-on experience in bench characterization, compliance testing, and fixture design, always striving for rigorous correlation between simulation and hardware. As a technical leader, you mentor others, drive technical reviews, and are committed to sharing your knowledge and standardizing best practices.

Your disciplined approach to documentation and reproducibility ensures that learning is captured and reused. You are proactive, detail-oriented, and thrive in dynamic environments, always seeking opportunities to optimize flows, influence architectural decisions, and deliver reliable, high-performance solutions. Your communication skills allow you to convey complex topics clearly to both technical and non-technical audiences, making you a valued partner to circuit, package, board, and product teams.

The impact you will have:

• Enable first-pass success of high-speed Ser Des IP and system integrations by defining robust SIPI signoff criteria and delivering validated, correlated methodologies.
• Reduce schedule risk by rapidly diagnosing complex cross-domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis.
• Raise the technical bar by mentoring others, standardizing best practices, and influencing architectural decisions for next-generation interconnects.
• Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments.
• Drive innovation in SIPI methodologies, enabling scalable, reusable flows across multiple programs and product lines.
• Foster a culture of collaboration and continuous improvement within the team and across partnering organizations.

What you'll need:

• B.S. (M.S./Ph.D. preferred) in Electrical/Electronic Engineering or related field.
• 1-2+ years of relevant experience in high-speed SI/PI for Ser Des links (silicon + package + board), preferably in interface IP or high-volume product development.
• Strong fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; comfortable translating system requirements into measurable/signoff criteria.
• Deep expertise with modeling, simulation and EM tools (HSPICE, Keysight ADS/System Vue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, Mathworks SIMULINK) and model formats (Touchstone, IBIS-AMI, SPICE, EM-based RLGC).
• Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working alongside validation/compliance teams.
• Proficiency in scripting/automation for flow enablement (Python preferred; MATLAB/TCL is a plus) and a disciplined approach to documentation and reproducibility.
• Demonstrated technical leadership: mentoring, design reviews, influencing cross-functional decisions, and communicating complex topics clearly to mixed audiences.

The team you'll be a part of:

You will join a global Ser Des/PHY design team, and will interact with package and board engineering, validation, and product teams to deliver high-performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment. Together, we drive innovation and enable our customers to achieve first-pass success in advanced system environments.

Rewards and benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during…