IC Layout Engineer

Employment Type:

Full-Time

Work Setting:
In-office/Hybrid

Work Location:

Hillsboro, Oregon (United States)

Work Hours:

Office hours

Find out more here:

We are seeking an experienced IC Layout Engineer to join our team in Hillsboro, OR specializing in technical analysis of AI and datacenter hardware. This role involves analyzing the physical design, layout, and manufacturing implementation of leading-edge integrated circuits, and being an active contributor in the planning, tools, and processes required to acquire this information. You'll examine competing hardware at the layout level: reading floor plans, standard-cell fabrics, analog blocks, and physical implementation choices directly from the die, and translating that physical evidence into actionable architectural and competitive insights.

This role requires a mix of technical expertise, design sensibility, and autonomy. You'll work independently and collaborate across our globally distributed team to examine and report on the design choices, optimizations, and trade-offs in competing hardware.

The role rewards curiosity. The strongest people in this work are drawn to investigation: taking apart what they could have helped design, connecting physical evidence to architectural intent and roadmap signals, and following threads beyond any single prior role.

• Conduct detailed physical design and layout analysis of AI and datacenter hardware, including GPUs, ASICs, CPUs, custom accelerators, high-speed I/O, memory subsystems, and their packaging
• Perform digital and analog floorplan analysis: identify functional blocks, partitioning strategy, hierarchy, power and clock distribution, and I/O placement from die-level imagery
• Assess standard-cell library choices, cell utilization, placement density, and area/timing/power optimization strategies across designs and process nodes
• Analyze analog/mixed-signal layout regions (Ser Des, PLLs, PHYs, power management) and interpret matching, isolation, and routing choicesli>
• Drive end-to-end teardown and characterization; operate the analytical toolchain and direct more specialized work as needed
• Identify competitive advantages, disadvantages, and generational changes in physical design, packaging, and system-level decisions
• Apply Design Technology Co-Optimization (DTCO) and System Technology Co-Optimization (STCO) reasoning to interpret layout trade-offs and process-design interactions
• Co-author technical research published by Semi Analysis, combining physical observation, cross-industry context, and argument all in your words
• Contribute to the growth and expansion of the lab's capabilities and output; bring your unique skills to a strong and expansive team

• We are hiring at all experience levels: 2+ years of industry experience in IC layout, physical design, place-and-route, custom/analog layout, or closely equivalent is preferred, but all exceptional candidates are encouraged to apply
• Genuine exposure to leading-edge parts
• Strong functional knowledge of digital and/or analog physical design flows (floor planning, placement, CTS, routing, and signoff) on advanced process nodes
• Working understanding of standard-cell architectures, cell utilization metrics, and area/power/performance optimization techniques
• Strong functional knowledge of AI and datacenter hardware architecture (GPUs, CPUs, accelerators)
• Direct experience in physical or electrical failure analysis, fault isolation, device debug, or related physical root-cause work, or strong aptitude to build it
• Understanding of Design Technology Co-Optimization (DTCO) principles
• Hands-on experience with, or strong aptitude for, semiconductor sample preparation and analytical tools such as precision polishing, FIB, SEM, and related electron-beam, X-ray, and compositional methods

• Experience with industry P&R and custom layout tools (e.g., Innovus, Fusion Compiler, Virtuoso) and reading GDS/OASIS-level detail
• Analog/mixed-signal layout expertise, including matching, shielding, guard rings, ESD, and high-speed interconnect layout
• Product design or manufacturing R&D in advanced packaging (2.5D / 3D, high-speed interconnects,…