Senior Design Verification Engineer

What You'll Do

At Viasat, you will be a member of a motivated team of system, design, and verification engineers developing cutting‑edge communications technology with a focus on high quality and time to market.

• Design verification planning including test plans
• Testbench development using System Verilog/UVM
• Hands‑on debug with the design team
• Ensuring quality via collection and analysis of coverage metrics, including code and functional coverage
• Managing regressions and compute resources
• Tool evaluation and license management
• Owning and driving technical issues to resolution
• Architecting design verification environments for ASICs and FPGAs
• Working with RTL, System, and software engineers to determine appropriate coverage closure for chip designs
• Creating drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs
• Maintaining and communicating program schedule and task tracking via Agile Jira
• Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, and working closely with RTL developers

• 8+ years of design verification experience, including UVM experience
• Experience in UVM testbench creation and usage
• Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field
• Experience with AI and agentic flow methodologies for design verification and chip development
• Foundational knowledge of digital logic and timing considerations
• Attention to detail, ability to follow process and coding guidelines, participate in code reviews, and accept feedback
• Experience with industry‑standard simulators such as Questa, Xcelium, and VCS
• Proven track record of work in UVM testbench development
• US citizenship
• Ability to travel up to 10%
• Must be able to obtain a secret clearance

• Strong written and verbal communication skills, ability to work with a geographically distributed team
• Object‑oriented programming experience
• Familiarity with designing and coding for testbench horizontal and vertical re‑use
• Familiarity with AI coding agents for design verification
• Ability to work independently, take initiative, and take ownership of tasks and results

$ – $ annually. For roles in San Jose, the San Francisco Bay Area and New York City metropolitan area, the base pay range is $ – $ annually.

Viasat is proud to be an equal‑opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, veteran status or any other applicable legally protected status or characteristic.

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