Digital ASIC Design Engineer

Digital ASIC Design Engineer – Aargau Canton | Hybrid

• Develop advanced digital ASICs for next-generation semiconductor systems
• Contribute across the full ASIC design flow:
  Behavioral modelling, RTL design, synthesis, timing analysis, optimization & sign‑off
• Collaborate with multidisciplinary experts including physicists, ASIC designers, electronics engineers & technicians
• Participate in practical laboratory activities: chip integration, testing & validation, electronics development, characterization work

• Master’s degree in Electronics, Microelectronics or a related field
• Strong digital ASIC design experience
• Good knowledge of Verilog, System Verilog or VHDL
• Understanding of RTL development flows, synthesis, timing analysis & digital design methodologies
• Experience with scripting / data tools such as Python & MATLAB
• Innovative mindset with curiosity for solving complex technical challenges
• Comfortable working independently and within collaborative engineering teams
• Strong English communication skills
• Nice to have: FPGA development experience, ASIC characterization or validation experience, PCB design exposure, analog ASIC knowledge, scientific instrumentation or particle physics experience

• Work on highly advanced technologies
• International engineering & research environment
• Cutting‑edge semiconductor systems
• Strong technical learning opportunities
• Innovative and collaborative culture