Principal Digital ASIC Design Engineer

Principal Digital Asic Designer

We are seeking talented and motivated individuals to tackle challenging engineering problems. As a Principal Digital Asic Designer, you will be responsible for designing high-performance digital Asics in advanced technologies
14nm Finfet, 22fdx, etc. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in this area while leading and mentoring junior engineers. We are specifically interested in candidates with a background in radiation-hardened design or in secure processor design. The successful candidate will contribute to Asic and Fpga development including architecture, analysis, design, and specification of Asics and IP blocks.

Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital Asic / Fpga efforts. Proficiency with Asic and Soc design and development process flows is preferred. Strong preference will be given to candidates with an understanding of radiation-hardened design, hardware security, signal or image processing, filter design and algorithm implementation in hardware.

Specific responsibilities include requirements capture and derivation, architecture definition and performance analysis, integration of third-party IP, design implementation using Systemverilog, Verilog or Vhdl, familiarity with Cdc, Lec and formal techniques, leading design and architecture teams, and top-level chip integration. This opportunity is located onsite in Odon, Indiana and will be hybrid.

Required qualifications include 15+ years of direct experience in the design of complex Fpgas and Asics, strong analysis and problem solving skills, fluency in Systemverilog/Verilog/Vhdl, experience in Cadence or equivalent digital Asic tool suite, experience with high-level design, simulation, and verification tools, experience with scripting languages Python/Perl and regular expressions, prior tapeouts or products released, background or experience in radiation-hardening, the design of space-grade electronics, and background or experience in hardware security or cryptography, e.g., encryption, key management, Trng/Drng, Pufs, root-of-trust, design obfuscation, etc.

Desired qualifications include familiarity with Soc trade space including processor selection, memory and bus implementation and architecture, experience with Linux/Unix OS, piping, batching, etc. Active security clearance preferred. Security requirement: applicants selected for this position will be required to obtain and maintain a government security clearance.