Sr Electrical Engineer - ASIC/FPGA; Onsite
Job in
Collins, Story County, Iowa, 50055, USA
Listed on 2026-07-08
Listing for:
Iowa State University Research Park
Full Time
position Listed on 2026-07-08
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Test Engineer, Systems Engineer
Job Description & How to Apply Below
Location: Collins
Job Description
We are looking for a Senior FPGA Engineer to be involved in the design, implementation, verification, and integration of a wide variety of high-performance digital ASICs, FPGAs, and circuit boards applied to computer graphics and supporting communication signal processing and information assurance products.
Location:
Cedar Rapids, IA
- Identify requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration.
- Recommend new tools and practices for continuous improvement in the group’s ASIC / FPGA design flow.
- Contribute to engineering estimates for new program pursuits.
- Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status.
- Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
- Active and transferable U.S. government issued security clearance is required prior to start date.
- U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.
- Experience in RTL coding and simulation in Verilog or VHDL.
- Experience in digital circuit architecture, design, resource tradeoffs, timing analysis, and timing closure.
- Experience in Testbench development for the verification of RTL blocks using System Verilog.
- Proficient using ASIC and/or FPGA simulation and synthesis tools (e.g., Model Sim, Synplify, Quartus, Vivado, or other FPGA-specific tools).
- Familiarity with revision control concepts and tools (e.g., Git, Subversion).
- Familiarity with best-practice chip-level verification techniques and languages (e.g., constrained random, functional coverage, System Verilog).
- Experience in ASIC / FPGA lab validation using advanced laboratory equipment.
- Experience in Design for Test (DFT) and manufacturability experience.
- Experience with Unix, scripting, C/C++, and/or Perl.
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