Analog​/Mixed Signal Verilog Modeling Design Engineer

Responsibilities

• Develop Digital‑Mixed Signal (DMS) models of analog IPs, such as touch controller AFEs, wireless power charging, health sensing AFEs, and satellite AFEs using System Verilog.
• Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.
• Understand Verilog‑AMS modeling language.
• Use System Verilog UDT/UDR nettype (using Cadence wreal or EEnet package).
• Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample‑and‑hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc.
• Understand good coding of RTL of digital design (e.g., clock divider, decoder, FSM) and testbench creation.
• Fully familiar with running SV vs. schematic verification for a given leaf SV model.
• Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor.
• Hands‑on skills in scripting languages (TCL/Perl/Python).
• Experience with AI tools such as Cursor, chip Agents to generate analog SV models and testbench based on a given design spec.

• Bachelor’s degree with 8+ years of related experience.
• Experience with analog‑mixed signal modeling.
• A strong foundation in analog circuit concepts.
• Proficiency with System Verilog, Verilog‑AMS, and scripting.
• Knowledge of CADENCE tools and AI‑generated models.

The annual base salary range for this position is $120,000 - $192,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental, and vision plans; 401(K) participation including company matching;
Employee Stock Purchase Program (ESPP);
Employee Assistance Program (EAP); company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

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