R&D Intern - FPGA​/RTL Design Engineer

Position: R&D Intern - FPGA/RTL Design Engineer - 2026
Company Overview

At Motorola Solutions, we believe that everything starts with our people. We're a global close-knit community, united by the relentless pursuit to help keep people safer everywhere. We build and connect technologies to help protect people, property and places. Our solutions foster the collaboration that's critical for safer communities, safer schools, safer hospitals, safer businesses, and ultimately, safer nations. Connect with a career that matters, and help us build a safer future.

Department Overview

Silvus Technologies was acquired by Motorola Solutions in 2025, and is now part of its ecosystem of safety and security technologies.

With deep roots in DARPA research, Silvus Technologies develops world-class advanced communications technologies that are reshaping the tactical communications landscape. From pure line-of-sight to extreme non-line-of-sight, Silvus radios form a self-healing, self-forming mesh network, enabling secure and reliable connectivity, including video and high-bandwidth data.

Job Description

THE OPPORTUNITY

The Intern - FPGA/RTL Design Engineer will report to the Senior Engineering heading our Irvine Engineering team with dotted line reporting to Technology Director, Wireless Systems. The successful individual in this role will learn and participate in the development of Silvus advanced research projects and will contribute to the efficient implementation of novel signal processing algorithms for Silvus MIMO wireless networking products.

These are exciting projects aimed at addressing challenging real-world communication needs.

This internship is full-time, fully onsite, Monday through Friday, at Silvus Technologies' Irvine office in the heart of Irvine near the vibrant Irvine Spectrum.

The following is a list of at least some of the current essential job functions of this internship opportunity.

ROLE, RESPONSIBILITIES, AND LEARNING OUTCOMES

* Working with system engineers and digital design architecting for wireless communication projects.

* RTL coding, simulation, and test bench development.

* FPGA synthesis and timing closure.

* Hardware verification and troubleshooting.

* Opportunities to further engage, learn, and develop skills as projects progress.

REQUIRED QUALIFICATIONS

* In-progress Bachelor's degree or preferably an in-progress graduate degree in Electrical Engineering, or a closely related technical field.

* Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.

* Knowledge of RTL design fundamentals using Verilog/VHDL.

* Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

* Must be a U.S. Citizen due to clients under U.S. government contracts.

* All employment is contingent upon the successful clearance of a background check and drug testing.

PREFERRED KNOWLEDGE,

SKILLS AND ABILITIES

* MATLAB coding experience.

* Understanding of digital signal processing.

* Understanding of digital/analog/RF circuits and PHY/MAC-layer concepts.

WORKING CONDITIONS &

PHYSICAL REQUIREMENTS

* Office environment.

* Occasional exposure to heat, cold, and allergens while performing tests or demonstrations in the field.

* While performing the duties of this job, the employee is required to do the following:

* Lift equipment up to 20 lbs. for the set-up of demonstrations and testing.

* Perform bending and reaching movements to place items on lower and higher shelves.

* Kneeling or squatting to access lower shelves.

* Must be able to lift up to 50 lbs. when receiving incoming part shipments.

* Walking/Moving in the labs.

CA Pay Range: $28.60 - $33.80 / hourly [in-progress Bachelor's degree]

CA Pay Range: $42.00 / hourly [in-progress Master's degree]

CA Pay Range: $55.60 / hourly [in-progress PhD degree]

Basic Requirements

* In-progress Bachelor's degree or preferably an in-progress graduate degree in Electrical Engineering, or a closely related technical field.

* Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

* Must be a U.S. Citizen due to clients under U.S. government contracts.

* All employment is contingent upon the successful clearance of a background check and drug testing.

Travel Requirements

None

Relocation Provided

None

Position Type

Intern

EEO…