ASIC RTL Design Engineer

New Grad
-ASIC RTL Design Engineer — Physical AI Compute

About Xcelerium

Xcelerium is building the computer foundation for real-time Physical AI — intelligent systems that must process rich sensor data, make decisions, and act under demanding real-world constraints of latency, bandwidth, power, size, and reliability.

We are developing a differentiated compute platform for workloads that span signal processing, AI/ML, linear algebra, optimization, control, and real-time decision-making. Our technology is designed for applications such as autonomous systems, robotics, wireless infrastructure, aerospace and defense, industrial automation, and edge AI.

Xcelerium is led by an experienced team of computer architects, chip designers, and technology leaders with deep backgrounds in advanced SoCs, wireless, AI/ML, compute, and high-volume semiconductor products. This is an opportunity to join a team building advanced silicon for a new class of real-world AI compute.

Primary location:
Irvine, CA

This is an on-site role.

Full-time, new graduate / entry-level

The expected base salary range for this role is $80K - $100K, plus eligibility for bonus/equity/benefits. Final compensation will depend on location, experience, and qualifications.

As a New Grad ASIC RTL Design Engineer — Physical AI Compute
, you will contribute to the design and implementation of advanced ASIC and SoC technology for Xcelerium’s next-generation compute platform.

This is a broad silicon design role for an exceptional early-career engineer who wants exposure to the full hardware development lifecycle — from architecture exploration and microarchitecture to RTL design, verification, physical design feedback, performance analysis, and silicon-quality design closure.

You will work with leading computer architects and expert chip designers to help build production silicon for a new class of real-time Physical AI compute.

We are looking for highly curious, technically strong, and ambitious engineers who want to learn quickly, contribute deeply, and grow into future leaders in computer architecture and silicon design.

• Contribute across the ASIC/SoC development lifecycle, including architecture exploration, microarchitecture, RTL design, verification, implementation feedback, and design closure.
• Help translate real-time Physical AI workload requirements into efficient hardware structures, datapaths, control logic, memory systems, and interconnects.
• Design and implement clean, synthesizable RTL in System Verilog or Verilog.
• Participate in high-performance datapath design for compute-intensive, bandwidth-intensive, and latency-sensitive workloads.
• Evaluate design tradeoffs involving latency, throughput, power, area, timing, programmability, reliability, and implementation complexity.
• Work hands-on with simulation, debug, lint, CDC, synthesis, static timing analysis, power analysis, and other ASIC development flows.
• Participate in verification activities, including test plan reviews, debug, assertions, observability, and design-quality improvements.
• Use physical design feedback to improve timing, frequency, area, power, and robustness on advanced silicon process technologies.
• Write clear design documentation, interface specifications, implementation notes, and debug summaries.
• Participate in technical design reviews and learn how advanced silicon is specified, designed, verified, implemented, and brought to production.

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent hands-on project or internship experience.
• Strong fundamentals in digital logic, synchronous design, finite state machines, pipelining, timing, and computer architecture.
• Experience writing RTL in Verilog or System Verilog through coursework, research, internship, FPGA work, ASIC projects, or personal projects.
• Familiarity with processor architecture, memory hierarchy, caches, buses, interconnects, datapaths, or SoC design concepts.
• Ability to write scripts or software in at least one language such as Python, C, C++, assembly, or a similar language.
• Strong…