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New Grad ASIC RTL Design Engineer — Physical AI Compute

Job in Irvine, Orange County, California, 92713, USA
Listing for: Xcelerium
Full Time position
Listed on 2026-05-18
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
Xcelerium is looking for a New Grad ASIC RTL Design Engineer in Irvine, CA. This full-time position involves contributing to advanced ASIC technology development. You’ll gain exposure to the hardware lifecycle, from architecture to implementation, working closely with experienced engineers. Ideal candidates possess a degree in Electrical Engineering or related fields, strong fundamentals in digital design, and coding experience in Verilog or System Verilog.

The salary range is $80K - $100K, plus benefits.
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