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Senior ASIC DV Engineer: PCIe & 400G MAC
Job in
Irvine, Orange County, California, 92713, USA
Listed on 2026-05-27
Listing for:
InSilico
Full Time
position Listed on 2026-05-27
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Job Description
Job Title:
Design Verification Engineer
Location:
Santa Clara, CA
Duration: 6 months (High possibility of an extension)
Senior DV engineer responsible for defining and implementing verification methodology and verifying in our next generation ASIC.
- PCIe verification background
- 400G MAC verification background
All your information will be kept confidential according to EEO guidelines.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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