Sr. IC Package Design Engineer; Silicon Engineering

Irvine, CA

Space

X was founded under the belief that a future where humanity is exploring the stars is fundamentally more exciting than one where we are not. Today Space

X is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At Space

X we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.

We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.

As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom in‑house ASICs and RFICs for digital beam formers and modems.

• Own and drive advanced package selection, new product BGA configuration and package structure
• Responsible for package/SIP layout, optimization, design verification and tapeout
• Interface and coordinate with cross‑functional groups throughout Space
  
  X on new product package selection, feasibility analysis and design
• Work cross‑functionally, understand trade‑offs, constraints, and optimizing silicon floor plan, bump and package pin out
• Simulate and optimize signal/power integrity and RF performance of the package design
• Drive methodology, innovations, and productivity improvements in package design

• Bachelor’s degree in electrical engineering, computer engineering, or physics
• 5+ years of experience with IC package design

• Experience with Co‑packed Optics (CPO)
• Thorough understanding of signal and power integrity fundamentals
• Substrate design experience for RF, digital, high‑speed and mixed‑signal die
• Experience with Cadence APD+/SIP or similar design tools
• Experience in package design electrical review, SI/PI analysis
• Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, ADS
• Experience in package design for manufacturing reviews
• Familiar with BGA package substrate technologies
• Strong problem solving skills with strong engineering fundamentals

• Ability to work extended hours or weekends as needed to meet mission‑critical deadlines

Pay range: RF Engineer/Senior: $ - $ per year.

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package  may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

• To conform to U.S. Government export regulations, applicant must be…