Validation Engineer

Position:
Mixed-Signal Verification Engineer

Location:

Irvine, CA Required

Skills and Experience:

• 8+ years of experience in mixed‑signal verification, modeling, or related fields
• Strong proficiency in System Verilog, including experience with UDT/UDR nettypes (Cadence Wreal or EEnet package) for analog modeling
• Deep understanding of analog circuit blocks, such as: LDOs, Transimpedance Amplifiers (TIAs), SAR ADC sample‑and‑hold (S/H), Comparators, DAC voltage converters, Buffering and amplification stages
• Experience modeling analog behavior in System Verilog – not just digital RTL, but capturing continuous‑time/real‑value analog behavior
• Hands‑on experience running SV vs. schematic verification for leaf‑level mixed‑signal models
• Proficiency with Cadence simulation and linting tools (xrun, ncsim, vcs) and analog schematic editors
• Scripting skills in TCL, Perl, or Python for automation and workflow optimization
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

We are seeking a highly skilled Mixed‑Signal Verification Engineer to join our team, responsible for developing Digital‑Mixed Signal (DMS) models of complex analog IPs. You will bridge the gap between analog design and digital verification, ensuring seamless integration and functional correctness of mixed‑signal designs across multiple product lines.