ASIC Design Verification Engineer

Overview

Broadcom is seeking experienced Design Verification engineers to work on PCIe and host interface technologies. The role involves verifying new designs that evolve rapidly, using constrained random verification methodologies, System Verilog, and UVM.

• Design, implement, and maintain Verification environments using System Verilog and UVM.
• Apply constrained random verification techniques and drive coverage closure.
• Collaborate with design engineers on PCIe and other host interfaces.
• Contribute to technical leadership and knowledge sharing within the team.

• Strong background in Design Verification for high-throughput Ethernet or similar technologies.
• Proficiency in System Verilog (TB structures, classes, SVA, etc.) and UVM.
• Experience with constrained random verification and coverage-driven closure.
• Self-motivated, strong teamwork skills, and ability to work well with others.
• Strong understanding of datapath flows.

• Experience with PCIe and third-party BFM.
• Object-oriented programming.
• Experience driving completion via coverage closure.

• System Verilog (TB structures – Class, SVA, etc.)
• UVM
• VCS, Incisive, or equivalent simulators
• Scripting:
  Python, Perl, or similar

• BSEE with 8+ years in related field, or MSEE with 6+ years.

Salary range: $91,200 – $152,000 per year, plus discretionary annual bonus and equity awards. Broadcom offers medical, dental, and vision plans; 401(K) with company matching;
Employee Stock Purchase Program;
Employee Assistance Program; paid holidays; paid sick leave and vacation; and compliance with Paid Family Leave and other leaves.

Broadcom is an equal opportunity employer. We consider applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, disability status, or other protected categories. We also consider qualified applicants with arrest and conviction records consistent with local law.