IC Design AI​/ML Silicon Debug & Yield Engineer

We need an engineer to own the end-to-end silicon diagnostic pipeline. You won’t just be looking at reports; you will be building the engines that generate them. In this role you will ingest massive volumes of scan failure data and process parameters, using AI-driven methodologies to find the "needle in the haystack" that is hindering our yield. Your goal is simple but ambitious: use AI/ML to transform millions of data points into actionable insights that drive aggressive yield ramps and shorten time‑to‑market.

• AI‑Driven Debug:
  Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck‑at, Transition) and correlate them with design‑for‑test (DFT) structures.
• Predictive Yield Modeling:
  Integrate high‑dimensional data—including fab process parameters, PCM (Process Control Monitoring), and E‑test data—to predict yield excursions before they hit the assembly line.
• Holistic Yield Analysis:
  Look beyond the bitcell. Analyze the interplay between design marginalities, voltage scaling, and manufacturing variations.
• Tool Orchestration:
  Evaluate and implement cutting‑edge AI‑based EDA tools for root‑cause analysis and systematic defect identification.
• Cross‑Functional Leadership:
  Act as the "translator" between the fab, design, and test teams, using data to prove where the silicon is diverging from the simulation.

• ASIC Design Engineering:
  Deep understanding of ASIC design, including logic circuits, memory, PLL/analog, place and route, STA, DFT, DFM, etc.
• The Debug Specialist:
  Knowledge of scan compression, BIST, ATPG patterns, and insights from shmoo plots.
• The Data Scientist:
  Proficient in Python (Pandas, Scikit‑Learn, PyTorch/Tensor Flow) for building custom analysis pipelines and understanding the underlying math.
• The Yield Strategist:
  Deep understanding of semiconductor manufacturing processes (FinFET nodes) and how physical defects manifest as logical failures.

• Education:
  
  Bachelor’s degree plus 8+ years of related experience OR Master’s degree plus 6+ years of related experience.
• Experience:
  
  3+ years in silicon debug, DFT, or yield engineering.
• Knowledge of deep sub‑micron (FinFET) effects, including IR drop, crosstalk, and process variation.
• Experience with pattern recognition, clustering (for defect binning), and regression models.
• Expertise in Python, SQL, and big data environments (Spark, Snowflake, etc.).
• Familiarity with industry‑standard yield management systems (e.g., PDF Solutions, Synopsys Yield Explorer, Cadence Clarity).

• Annual base salary range: $108,000 – $192,000.
• Eligible for discretionary annual bonus in accordance with the relevant plan documents.
• Eligible for equity in accordance with the equity plan documents and equity award agreements.
• Comprehensive benefits package:
  Medical, dental, vision plans; 401(k) with company matching;
  Employee Stock Purchase Program (ESPP);
  Employee Assistance Program (EAP); company‑paid holidays; paid sick leave and vacation time; paid family leave and other applicable leaves of absence.

Broadcom is proud to be an equal‑opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.