IC Design AI​/ML Silicon Debug & Yield Engineer

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Job Description:

We need an engineer to own the end-to-end silicon diagnostic pipeline. You won't just be looking at reports; you will be building the engines that generate them. In this role, you will ingest massive volumes of scan failure data and process parameters, using AI-driven methodologies to find the "needle in the haystack" that is hindering our yield.

Your goal is simple but ambitious:
Use AI/ML to transform millions of data points into actionable insights that drive aggressive yield ramps and shorten time-to-market.

Key Responsibilities

* AI-Driven Debug:
Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.

* Predictive Yield Modeling:
Integrate high-dimensional data-including Fab process parameters, PCM (Process Control Monitoring), and E-test data-to predict yield excursions before they hit the assembly line.

* Holistic Yield Analysis:
Look beyond the bitcell. You'll analyze the interplay between design marginalities, voltage scaling, and manufacturing variations.

* Tool Orchestration:
Evaluate and implement cutting-edge AI-based EDA tools for root-cause analysis and systematic defect identification.

* Cross-Functional Leadership:
Act as the "translator" between the Fab, Design, and Test teams, using data to prove where the silicon is diverging from the simulation.

The Ideal Candidate

* ASIC Design Engineering:
Deep understanding of ASIC design, including logic circuits, memory, PLL/Analog, Place and route, STA, DFT, DFM, etc.

* The Debug Specialist:
You know your way around scan compression, BIST, and ATPG patterns. You understand what a "shmoo plot" is telling you about a timing marginality.

* The Data Scientist:
You don't just "use" tools; you understand the math. You are proficient in Python (Pandas, Scikit-Learn, PyTorch/Tensor Flow) for building custom analysis pipelines.

* The Yield Strategist:
You have a deep understanding of semiconductor manufacturing processes (FinFET nodes) and how physical defects manifest as logical failures.

Technical Requirements

Bachelor's degree plus 8+ years of related experience OR Master's degree plus 6+ years of related experience

3+ years in Silicon Debug, DFT, or Yield Engineering.

Knowledge of Deep Sub-micron (FinFET) effects, including IR drop, crosstalk, and process variation

Experience with Pattern Recognition, Clustering (for defect binning), and Regression models.

Expertise in Python, SQL, and big data environments (Spark, Snowflake, etc.).

Familiarity with industry-standard yield management systems (e.g., PDF Solutions, Synopsys Yield Explorer, or Cadence Clarity).

Additional

Job Description:

Compensation and Benefits

The annual base salary range for this position is $108,000 - $192,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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