Sr. ASIC DFT Engineer; Silicon

SR. ASIC DFT ENGINEER (SILICON ENGINEERING)

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering and ASIC implementation). In this role, you will be developing next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.

Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

• Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
• Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
• Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck‑at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows.
• Run and debug non‑timing and SDF annotated gate‑level simulations
• Create and validate DFT patterns for post‑silicon bringup and also help with ATE debug through all cycles of silicon characterization
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

• Bachelor’s degree in electrical engineering, computer engineering, or physics
• 5+ years of experience in semiconductor Design For Test (DFT) engineering, post‑silicon validation, and/or production testing

• Master’s or PhD in electrical engineering, computer engineering, physics, or related engineering field
• Extensive experience in post‑silicon bringup, including silicon debug, failure analysis, and yield optimization on complex SoCs or ASICs
• Hands‑on experience with Automated Test Equipment (ATE) platforms (e.g., Teradyne, Advantest) for high‑volume manufacturing test development and debug
• Experience collaborating with cross‑functional teams (e.g., design, verification, and manufacturing) to ensure DFT features meet production requirements, utilizing Siemens Tessent workflows
• Knowledge of industry standards for testability (e.g., IEEE 1500, 1687) and experience with low‑power DFT techniques using Siemens Tessent
• Experience with In‑System Test (IST), boundary scan (IEEE 1149.1), functional testing in embedded systems, or board‑level diagnostics, preferably using Siemens Tessent tools
• Hands‑on experience with Tessent Streaming Scan Network
• Experience with cell‑aware fault models in ATPG
• Excellent problem‑solving skills, with the ability to analyze complex test failures and implement corrective actions
• Strong communication skills for documenting test strategies, reporting results, and presenting to stakeholders
• Ability to work in a fast‑paced environment, handling multiple projects and adapting to evolving technology nodes (e.g., 7nm and below)

• Ability to work extended hours and weekends as needed to meet critical milestones

Pay Range:
Level 1: $125,000 - $150,000
Level 2: $145,000 - $175,000

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package  may also be eligible for long‑term incentives, in the form of company stock or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company…