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RTL Design Engineer -Gen ASIC​/FPGA; Starlink

Job in Irvine, Orange County, California, 92713, USA
Listing for: SPACE EXPLORATION TECHNOLOGIES CORP
Full Time position
Listed on 2026-06-07
Job specializations:
  • Engineering
    Engineering Design & Technologists, Systems Engineer
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below
Position: RTL Design Engineer for Next-Gen ASIC/FPGA (Starlink)
A leading aerospace company in Irvine, CA, is seeking an RTL Design Engineer to design ASICs and FPGAs for Starlink projects. The ideal candidate will collaborate with cross-disciplinary teams to create cutting-edge solutions that enhance connectivity. A Bachelor's degree in Electrical Engineering or related field and at least one year of experience in RTL design are required.

This role offers competitive compensation, comprehensive benefits, and opportunities for professional growth.
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