RTL Design Engineer; Silicon Engineering

Irvine, CA

Space

X was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today Space

X is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At Space

X we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.

We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.

Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

• Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participating in integration tasks using Verilog/System Verilog.
• Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high‑level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring‑up and validation.
• Engage in high‑level architectural design for FPGA and ASICs.
• Collaborate with cross‑functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics.
• 1+ years of experience in RTL Design using System Verilog, Verilog or VHDL.

• Master’s in Electrical/Computer Engineering or related field.
• Proficiency in Python for scripting.
• Experience with EDA tools such as HDL simulators.
• Experience and understanding of AXI/AHB/APB protocols.
• Strong foundation in electrical engineering fundamentals.
• Ability to work in a dynamic environment with changing needs and requirements.
• Team‑player, can‑do attitude and ability to work well in a group environment while still contributing on an individual basis.
• Demonstrated ability to work in a highly cross‑functional role.
• Enjoys being challenged and learning new skills.

• Ability to work extended hours or weekends as needed for mission critical deadlines.

Pay range: ASIC Design Engineer/Level I: $ - $ per year
ASIC Design Engineer/Level II: $ - $ per year

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package  may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per…