Physical Design Engineer II; Silicon Engineering

Physical Design Engineer II (Silicon Engineering)

Irvine, CA

Space

X was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today Space

X is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.

Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floor planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 3+ years of professional experience working on RTL2
  
  GDSII physical design and/or physical design flow development

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub‑micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Self‑driven individual with a can‑do attitude, willing to learn, and an ability to work in a dynamic group environment

• Ability to work extended hours and weekends as needed to meet critical project milestones

Pay range:
Physical Design Engineer/Level II: $145,000 - $175,000 per year. Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package. You may also be eligible for long‑term incentives, in the form of company stock, stock options, or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long‑term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident, (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

Space

X is an Equal Opportunity Employer; employment with Space

X is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of Space

X’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to