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ASIC RTL Design Engineer SoCs & RISC-V

Job in Irvine, Orange County, California, 92713, USA
Listing for: Xcelerium
Full Time position
Listed on 2026-06-20
Job specializations:
  • Engineering
    Hardware Engineer, Quality Engineering, Electronics Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: ASIC RTL Design Engineer: High-Performance SoCs & RISC-V

Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.

This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/System Verilog and a passion for technology will be essential for success in this innovative environment.

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