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Senior ASIC Verification Engineer; SV/UVM – Equity
Job in
Irvine, Orange County, California, 92713, USA
Listed on 2026-06-26
Listing for:
Broadcom
Full Time
position Listed on 2026-06-26
Job specializations:
-
Engineering
Test Engineer
Job Description & How to Apply Below
Broadcom in Irvine, California is seeking a Constrained Random Design Verification Engineer to join a stable team developing silicon products for Ethernet systems. The role involves verifying new designs and collaborating with global teams to develop cutting-edge products.
The ideal candidate will have a Bachelor's degree with 12+ years of experience, or a Master's with 10+, or a PhD with 3+. Strong teamwork, System Verilog and UVM skills are essential. The position includes a competitive salary and comprehensive benefits package.
#J-18808-LjbffrPosition Requirements
10+ Years
work experience
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