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Senior Chip Verification Architect — Chip Signoff

Job in Irvine, Orange County, California, 92713, USA
Listing for: United States Digital Space LLC
Full Time position
Listed on 2026-07-03
Job specializations:
  • Engineering
    Test Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 160000 - 225000 USD Yearly USD 160000.00 225000.00 YEAR
Job Description & How to Apply Below
Position: Senior Chip Verification Architect — Full-Chip Signoff

United States Digital Space LLC is seeking a Sr. Full Chip Physical Verification Engineer in Irvine, California. The role demands expertise in ASIC verification and physical design to enhance Starlink’s global connectivity. The engineer will collaborate with teams across multiple disciplines to drive the development of cutting-edge silicon.

The position offers a competitive compensation range from $160,000 to $225,000 annually, along with comprehensive benefits including 401(k), medical coverage, and potential stock options.

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Position Requirements
10+ Years work experience
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