Senior Principal Digital Design Engineer

Responsibilities

Max Linear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following:

• Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators)
• Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL
• Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan
• Lead improvements to design methodology to maximize efficiency and predictability
• RTL implementation in System Verilog of communication/DSP/packet-processing functions
• Block-level verification including creation of Verilog or UVM test benches
• System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis
• Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis
• Perform design quality checks including lint, CDC and DFT-readiness checks
• Support emulator-based verification including debug of SW driven test cases
• Post silicon bring‑up support and debug in lab; support system integration and production testing
• Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center So Cs

• Expert in digital design including micro‑architecture definition and area/power/timing optimization
• Solid understanding of high‑speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations
• Experience with performance modeling and analysis, including performance constraint identification and optimization
• Extensive experience with ASIC front‑end design flow including RTL coding (System Verilog), directed/randomized verification, simulation/emulation debug, lint/CDC checks, synthesis, power analysis and timing closure support
• Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed‑point ASIC implementation a plus
• Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs
• Strong logical and creative problem‑solving skills with excellent analytical and debugging skills
• Solid written and verbal communication skills
• Flexibility to ramp quickly on new technologies, products, and methodologies
• Self‑motivated with ability to provide leadership and work effectively in fast‑paced environment
• BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience

Max Linear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock‑based compensation.

Max Linear's good faith estimate starting base salary range is: $186,000 to $228,000

Annually

We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.

The actual starting base salary will be determined by certain role‑related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all‑inclusive list as some roles may require unique skills or experience.

Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.