Digital Design Principal Engineer​/Manager

Digital Design Principal Engineer/Manager

Irvine, California, United States

Inno Phase Inc., DBA Green Wave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting‑edge solutions, powered by the Hermes
64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose‑built silicon that is the heart of ORAN‑based active antenna arrays.

Headquartered in San Diego, California, Green Wave Radios™ has established itself as a pioneer in delivering power‑efficient digital‑to‑RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, Green Wave Radios™ continues to push the boundaries of radio technology and innovation.

We’re looking for an experienced Principal Engineer/Manager to lead a small, high‑impact team building next‑generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You’ll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high‑performance programmable logic with embedded Linux‑based wireless communications software. This is a senior technical leadership and management role with direct influence on our market‑leading cellular infrastructure products, working hands‑on alongside experts across design, verification, firmware, and system engineering.

• Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight
• Own solution architecture end‑to‑end—taking marketing requirements and translating to product specifications through production‑quality programmable logic design, verification and hardware validation
• Drive architecture / micro‑architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs
• Collaborate with system engineering on Radio product specifications, ensuring alignment across the company
• Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones
• Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock‑domain crossing checks, and formal verification
• Collaborate with embedded Linux‑based wireless communications software team that complements the FPGA/ASIC logic layer

• 20+ years of experience in FPGA and SoC development and mass production, including a proven track record in a technical leadership and management role
• MS or PhD in Electrical Engineering or equivalent
• Deep expertise in Verilog and System Verilog, and front‑end tooling (simulation, linting, CDC, formal verification)
• Hands‑on experience with packet processing designs including buffering, routing, transposing, combining, framing/de‑framing packet based formats (e.g. Ethernet, O‑RAN/eCPRI, etc)
• Hands‑on experience with AMBA AXI/AHB/APB bus protocol specification and implementation
• Proven ability to define constraints, run synthesis and static timing analysis, and own a complete front‑to‑back AMD (Xilinx Vivado) FPGA implementation flow
• Working knowledge of DFT/DFM, SCAN ATPG, BIST, and fault coverage analysis
• Proficiency in System Verilog and other advanced design verification methodologies
• Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python
• Strong communication and presentation skills; ability to drive results under aggressive schedules across cross‑functional teams

• Experience developing cellular infrastructure radio products, particularly 10/25
  
  Gbps Ethernet eCPRI connectivity to the DU and interface to RF ASICs.
• Familiarity with O‑RAN FS7.2x specifications or eCPRI/CPRI front haul protocols
• Understanding of Array based radios including AAU and mMIMO
• Exposure to AI‑assisted EDA tools for synthesis, timing analysis, or verification (e.g., AI‑driven placement/routing assistants, ML‑based timing closure prediction, AI‑guided power analysis)
• Experience using…