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Sr. FPGA Design Engineer​/DSP​/ASIC​/Vivado IDE​/Onsite​/Irvine in Irvine

Job in Irvine, Orange County, California, 92713, USA
Listing for: Energy Jobline ZR
Full Time position
Listed on 2026-07-27
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 140000 - 200000 USD Yearly USD 140000.00 200000.00 YEAR
Job Description & How to Apply Below
Position: Sr. FPGA Design Engineer / DSP / ASIC / Vivado IDE / Onsite / Irvine in Irvine

Job Description A well-established security company that helps build technology to help protect our communities. Their technology is pivotal to creating software that helps create safer schools, hospitals and ultimately a safer nation. They are currently looking for several FPGA Design Engineers.

The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D. The right candidate should have strong FPGA Design experience, DSP / Digital Signal Processing, binary arithmatic, clock-domain, Xilinix and Vivado IDE.

THIS POSITION REQUIRES A U.S CITIZENSHIP STATUS - CANDIDATES MUST BE ABLE TO WORK ONSITE 4 DAYS A WEEK IN IRVINE CA OR LOS ANGELAS

ROLE AND RESPONSIBILITIES
  • Digital design architecting for wireless communication projects.
  • Fixed point design of signal processing blocks while working with systems engineers.
  • RTL coding, simulation, and test bench development.
  • FPGA synthesis and timing closure.
  • Hardware verification and troubleshooting; familiarity with logic analyzers.
  • Provide support to the RF and Software Engineering Teams.

REQUIRED QUALIFICATIONS

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.
  • Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with a Master’s of Science degree; 2 years of FPGA design experience with a PhD degree.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.

SKILLS, AND ABILITIES

  • Master of Science degree in Electrical Engineering (MSEE).
  • Basic MATLAB skill.
  • Experience with communication systems on FPGA or ASIC designs.

THE OFFER

  • 140-200k base salary based on experience level
  • Strong Bonuses
  • Relocation expensis
  • 401k
  • Full - Health Medical Dental benefits
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