Senior Design Engineer

As a Senior Hardware Design Engineer, you will be responsible for:

• Designing micro-architectures and RTL implementations to meet requirements provided by Algorithm and System Architecture teams, while providing feedback to improve RTL design efficiency and performance.
• Implementing FPGA and/or ASIC designs using industry-standard methodologies, design flows, and tools, including the development of block-level and system-level test benches.
• Deploying designs onto leading FPGA development platforms for validation, debugging, and system integration.
• Contributing to engineering best practices, methodologies, processes, and design techniques, while identifying opportunities to improve design efficiency, quality, and overall product performance.
• Collaborating with cross-functional teams throughout the design lifecycle to ensure successful project delivery.

• Expert knowledge of Verilog and System Verilog for complex ASIC and FPGA development.
• Minimum 5 years of industry experience designing and delivering successful FPGA and/or ASIC solutions, including implementations involving multi-Gbps high-speed communication, connectivity protocols, or advanced digital signal processing applications.
• Strong background in digital design for ASIC and FPGA technologies.
• Proven ability to deliver high-quality designs within demanding project schedules.
• Experience optimizing timing closure, hardware resource utilization, and performance for high-throughput data or signal processing applications.
• Knowledge of power management techniques, synthesis, and timing analysis.
• Demonstrated success collaborating across multidisciplinary engineering teams to deliver integrated solutions.
• Experience producing technical documentation, including design specifications, verification plans, and user guides.
• Proficient in the use of EDA tools for simulation, verification, and synthesis.
• Knowledge of wireless communications systems and digital signal processing algorithms, including areas such as error correction, equalization, channel estimation, and beamforming.
• Familiarity with AMBA/AXI bus protocols.
• Understanding of UVM methodologies or practical experience using UVM for IP verification.
• Experience with C++ and/or SystemC for modelling and system integration.
• Experience working with high-speed interfaces such as PCIe or JESD.
• Knowledge of scripting languages such as Python.
• Understanding of project delivery methodologies across the design lifecycle, including Agile and Waterfall approaches, requirements capture, and traceability.
• Experience with FPGA development platforms and associated tool chains, and/or ASIC backend implementation tools from leading EDA vendors.

• Opportunity to work on cutting-edge ASIC and FPGA development projects.
• Exposure to advanced digital communications and high-performance signal processing technologies.
• Collaborative engineering environment with opportunities to influence design methodologies and product development.
• Career growth within a technically challenging and innovative setting.