Lead Design Verification Engineer - R10216127

Staff Lead Design Verification Engineer

Northrop Grumman is seeking a Staff Lead Design Verification Engineer to join the Systems Engineering Integration & Test (SEIT) department and lead verification efforts for state‑of‑the‑art Digital Logic (High Speed Serial). The role involves working with physicists, design engineers, and superconducting foundry engineers to translate cutting‑edge technologies into high‑performance computing systems.

Eligibility & Logistics

• U.S. citizenship required.

• Relocation assistance may be available.

• Clearance type: SCI.

• Travel: 10% of the time.

• Lead the verification team for debug, emulation, and test development.
• Create comprehensive test‑benches for behavioral simulation.
• Design and implement verification strategies for complex digital systems.
• Ensure RTL implementation satisfies precise design specifications.
• Conduct in‑depth behavioral simulations across ASIC and FPGA.
• Generate and execute advanced UVM test cases; achieve 95% code coverage on critical metrics.
• Perform detailed code coverage analysis (statement, expression, branch, toggle coverage).
• Utilize functional and timing simulation tools to verify logical behavior and implementation accuracy.
• Identify and resolve signal delay and performance issues in gate timing requirements.
• Develop UVM simulation environments.
• Collaborate with design teams to validate RTL, provide feedback, participate in design reviews, and lead verification planning.
• Mentor junior verification engineers and contribute to continuous improvement of verification methodologies.

• Bachelor’s degree in Computer Engineering, BSEE, or comparable STEM degree plus 12 years of industry experience in a design verification role; or Master’s degree plus 10 years; or PhD plus 7 years.
• Proven experience leading verification teams and managing the full life‑cycle of functional verification methodology.
• Specialized experience with multiple tape‑outs.
• Expert‑level proficiency in Verilog, VHDL, and System Verilog.
• Extensive knowledge of RTL design methodologies, behavioral simulation techniques, and code coverage strategies.
• Experience with industry‑standard EDA tools (Cadence, Synopsys, Mentor Graphics).
• Experience with UVM, regression, and automation framework development.
• Willingness to obtain and maintain a security clearance.

• Advanced degrees in Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.
• Experience with advanced gate‑level simulations.
• Experience managing schedule, cost, metric reporting, and trade studies.

Primary level salary range: $ – $. Base salary is determined by scope, responsibilities, experience, education, skills and market conditions.

Employees may be eligible for overtime, shift differential, bonuses, long‑term incentives, and a variety of benefits including health insurance, life and disability insurance, savings plan, company‑paid holidays, and paid time off.

Estimated 20 days from posting date; the timeline may vary based on business needs and candidate availability.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. U.S. citizenship is required for positions with government clearance.