Design Verification Engineer

Founded in 2004, Montage Technology is a leading IC design company dedicated to providing high-performance, low-power IC solutions for cloud computing and data center markets. Montage Technology provides industry leading DDR2 to DDR5 memory interface products for the demanding cloud computing and data center markets. Our robust product portfolio includes the critical components required by the memory modules, such as a Registering Clock Driver (RCD), Data Buffer (DB), SPD EEPROM with Hub (SPD Hub), Temperature Sensor (TS) and Power Management IC (PMIC).

Compliant with JEDEC specifications, these products are designed for a variety of memory modules such as RDIMM, LRDIMM, NVDIMM, UDIMM, SODIMM, MRDIMM, etc., to enable high-speed, large-capacity, high-reliability and low-power memory solutions for high-performance computing.

Job Description:

We are looking for Verification Engineers who will help develop system level UVM test benches. In this role, you’ll work hands‑on in pre-silicon verification for DDR5 and early DDR6 DIMM systems and PMIC IP. You’ll be dealing with real system-level complexity, finding bugs before silicon, and building verification environments that get reused across products. You’ll also have room to explore AI‑assisted verification ideas to help close coverage faster, speed up debug, and make regressions less painful.

• Take ownership of system-level verification for DDR5 and early DDR6 DIMM subsystems and PMIC IP, with a focus on correctness, corner cases, and protocol behavior.
• Build, maintain, and improve UVM System Verilog test benches and verification infrastructure that scale across product generations.
• Create directed and constrained-random stimulus, functional coverage, assertions, and automation to close coverage efficiently.
• Review architecture and specs with a verification mindset, calling out ambiguities, risks, and missing coverage early.
• Work closely with validation and component test teams to make sure pre-silicon coverage lines up with post-silicon debug and bring-up needs.
• Support silicon debug led by Validation Engineering by reproducing issues in simulation and helping narrow down root causes.
• Try out and apply AI-assisted verification tools and workflows (stimulus generation, coverage analysis, regression triage, debug help) where they make sense.
• Keep regressions healthy, debug failures, and push fixes that stick.
• Help grow the team by sharing knowledge, reviewing work, and mentoring junior engineers.

• BS or MS in Electrical Engineering, Computer Engineering or equivalent;
• 5+ years of relevant work experience;
• Good understanding of CMOS circuit design;
• Strong understanding and hands on experience in building UVM Test benches from scratch;
• Proficient with digital and analog simulation tools, e.g.: VCS, Xcellieum, Verdi etc.;
• Excellent debugging and problem solving skills;
• Strong understanding of DDR5 protocol or CXL 2.0 spec.